1. Field of the Invention
The present invention relates to a semiconductor memory device, especially relates to a DDR-SDRAM (Double Data Rate synchronous Dynamic Random, Access Memory)
2. Description of the Related Art
Recently, SDRA operating in synchronization with a clock signal for a main storage of a computer is disclosed in Japanese Laid Open Patent applications (JP-P2000-40363A, JP-P2000-132966A, JP-P2002-025255A, JP-P2000-268565 and JP-P2001-093280: first to fifth conventional examples). In order to improve a data transmitting speed, DDR-SDRAM and DDRII-SDRAM become general; which are characterized by that (1) a 2n-bit pre-fetch method (n is an integer) is adapted and (2) a data is latched in response to a strobe signal instead of a clock signal. In the 2n-bit pre-fetch method, data of twice of the number n of inputted/outputted bits are read and written at a same.
The DDR-SDRAM adapting the 2n-bit pre-fetch method will be described bellow. FIG. 1 shows the circuit configuration of the semiconductor memory device of the first conventional example. A read operation as a memory operation (the memory access) will be described. The semiconductor memory device of the first conventional example is composed of memory cell arrays 1 and 2, row decoder circuits 3 and 4, sense amplifier circuits 5 and 6, an address receiving circuit 7, an address latch circuit 8, an X address buffer circuit 9, a Y-address buffer circuit 10, a command receiving circuit 11, a command decoder circuit 12, a clock receiving circuit 13, a column control circuit 14, a data receiving circuit 15, a data strobe receiving circuit 16, a data latch circuit 17, a write buffer circuit 18, write amplifier circuits 19 and 20 and column decoder circuits 21 and 22. This semiconductor memory device is provided for a computer. A CPU (Central Processing Unit) and a clock generator (both are not shown) are also provided for the computer.
The memory cell array 1 is provided on the side of even and the memory cell array 2 is on the side of odd. Both of the memory cell arrays 1 and 2 include memory cells in a matrix manner N rows and M columns (both of N and M are natural numbers). The N rows in the memory cell array 1 are connected to word lines, respectively. The word lines are connected to the row decoder circuit 3. The M columns in the memory cell array 1 are connected to bit lines, respectively. The bit lines are connects to the sense amplifier circuit 5 and column selection lines CSL. The column selection lines CSL are connects to the column decoder circuit 21. The N rows in the memory cell array 2 are connected to word lines, respectively. The word lines are connects to the row decoder circuit 4. The M columns in the memory cell array 2 are connected to a bit line. The bit lines are connected to the sense amplifier circuit 6 and column selection lines CSL. The column selection lines CSL are connected to the column decoder circuit 22.
The clock receiving circuit 13 inputs a clock signal clock generator to convert to a internal clock signal ICLK, and then outputs the internal clock signal ICLK to the address latch circuit 8, the Y-address buffer circuit 10, the command decoder circuit 12, the column control-circuit 14 and the data latch circuit 17. The address, receiving circuit 7 inputs an address ADD from the CPU and converts to an address CADD in accordance with an internal command, and then outputs the address to the address latch circuits 8 in response to the clock signal CLK. The address latch circuit 8 receives the address CADD from the address receiving circuit 7 in response to the clock signal CLK, and outputs as an address IA to the X-address buffer circuit 9 and Y-address buffer circuit 10 in synchronization with the internal clock signal ICLK.
The command receiving circuit 11 inputs a CSB (chip selection bar) signal, a RASB (row address strobe bar) signal, a CASB (column address strobe bar) signal and a WEB (write enable bar) signal from the, CPU in response to the clock signal CLK. Then, the command receiving circuit 11 inverts these signals into a CCS signal, a CRAS signal, a CCAS signal and a CWE signal to output them to the command decoder circuit 12.
The command decoder circuit 12 inputs the CCS signal, the CRAS signal, the CCAS signal, and the CWE signal and outputs an active Y-address buffer control signal YAL to the Y-address buffer circuit 10 and the column control circuit 14 in synchronization with the internal clock signal ICLK. Also, the command decoder circuit 12 outputs an active Y-address buffer control signal NYAL to the Y-address buffer circuit 10 and the column control circuit 14 synchronization with the next clock of the internal clock signal ICLK. When a CWE signal indicates a write operation, the command decoder circuit 12 outputs an active command signal WBST to the column control circuit 14 in synchronization with the internal clock signal ICLK. Also, when the CWE signal indicates a read operation, the command decoder circuit 12 outputs an inactive command signal WBST to the column control circuit 14 in synchronization with the internal clock signal ICLK.
An X-address buffer circuit 9 inputs an address IA from the address latch circuit 8. When the address IA is X-address (a row address), an address XA is outputted to the row decoder circuits 3 and 4. The row decoder circuits 3 and 4 decode the address XA supplied from the X-address buffer circuit 9 and drive word lines connected to the memory cells of the memory cell arrays 1 and 2 in response to the address XA. The Y-address buffer circuit 10 receives the address IA from the address latch circuit 8 in synchronization with the internal clock signal ICLK, and outputs the address YA to the column decoder circuits 21 and 22 in response to the Y-address buffer control signals YAL and NYAL, when the address IA is a Y-address (a column address).
When a command signal WBST from the command decoder circuit 12 is active, the column control circuit 14 inputs the Y-address buffer control signal YAL, and outputs an active write buffer control signal W0 to the write buffer circuit 18 in response to the Y-address buffer control signal YAL. Also, when the command signal WBST supplied from the command decoder circuit 12 is inactive, the column control circuit 14 inputs the Y-address buffer control signal NYAL, and outputs an active write buffer control signal W0 to the write buffer circuit 18 in synchronization with the internal clock signal ICLK.
The column control circuit 14 outputs an active column selection line control signal YSEL to the column decoder circuits 21 and 22 in response to the Y-address buffer control signals YAL and NYAL. When the command signal WBST is active to indicate a write operation, the column control circuit 14 outputs the active write amplifier control signal WAE in response to the Y-address buffer control signals YAL and NYAL. The column decoder circuits 21 and 22 decode the address YA from the Y-address buffer circuit 10 and drive the column selection line CSL connected to the memory cells of the memory cell arrays 1 and 2 in response to the address YA.
The data receiving circuit 15 receives a data DQ from the CPU in response to the clock signal CLK, and outputs the data DQ as a data CDQ to the data latch circuit 17. The data strobe receiving circuit receives a data strobe DQS in synchronization with the clock signal CLK from the clock generator, and outputs a data strobe CDQS to the data latch circuit 17. The data latch circuit 17 latches the data CDQ from the data receiving circuit 15 in response to the data strobe CDQS, and outputs data IDQ to the write buffer circuit 18 in synchronization with the internal clock signal ICLK. The write buffer circuit 18 outputs a WBUS signal to the write amplifier circuits 19 and 20 in response to light buffer control signal W0 from column control circuit 14. The write amplifier circuits 19 and 20 outputs the WBUS signal outputted from the write buffer circuit 18 as a write input data IO in response to the write amplifier control signal WAE from column control circuit 14. The sense amplifier circuits 5 and 6 supply the bit line with a voltage and amplify the electric potential on the bit lines connected to the memory cell of memory cell arrays 1 and 2, when the word lines have been driven by row decoder circuits 3 and 4.
Next the write operation of the semiconductor memory device of the first conventional example will be described. In the initial operation, the address receiving circuit 7 inputs the X address as an address ADD in synchronization with the clock signal CLK and output the address CADD (address XA), the address latch circuit 8 latches the address CADD in synchronization with the internal clock signal ICLK and output the address CADD (address, XA) as the address IA. Also, the X-address buffer circuit 9 inputs the address IA (address XA) and outputs the address XA to the row decoder circuits 3 and 4, the row decoder circuits 3 and 4 decode the address XA, from the X-address buffer circuit 9 and drive the word lines in accordance with the address XA (the X-address). Moreover, the sense amplifier circuits 5 and 6 supply the bit lines with a voltage and amplify the electric potentials on the bit lines connected to the memory cells of the memory cell arrays 1 and 2, when the word lines have been driven by the row decoder circuits 3, 4.
In case of the write operation, the WEB signal indicates the write operation, and the command receiving circuit 11 inputs the CSB, RASB, CASB, WEB signals in synchronization with the clock signal CLK, then outputs the commands the CCS, CRAS, CCAS, CWE signals to the command decoder circuit 12, and the address receiving circuit 7 inputs the address Y0 as address ADD in synchronization with the clock signal CLK, and outputs the address CADD (address Y0) to the address latch circuit 8. Also, the data receiving circuit 15 inputs a data D0 (even), D1 (odd), D2 (even), D3 (odd) as data DQ in synchronization with the clock signal CLK and outputs the data CDQ (data D0, D1, D2, D3 ), a bust length at this time is 4.
The write operation will be now described bellow referring to FIG. 1 and FIG. 2. The timing when the command receiving circuit 11 inputs the write command in synchronization with the clock signal CLK is supposed to be P0. The clock receiving circuit detects the rising edge of the clock signal CLK when the clock receiving circuit inputs the clock signal CLK at the timing P0, P1, P2, P3, P4, . . . . Then, the clock receiving circuit outputs the internal clock signal ICLK as an one-shot pulse signal at the timing T0, T1, T2, T3, T4, . . . . The data strobe receiving circuit 16 inputs the data strobe DQS in synchronization with the clock signal CLK and outputs the data strobe CDQS to the data latch circuit 17 at the timing P0, P1, P2, P3, P4, . . . . The pulses of the internal clock signal ICLK are outputted to have a time differences of (P0−T0), (P1−T1), (P2−T2) (P3−T3), (P4−T4), . . . from the clock signal CLK.
The data latch circuit 17 receives a data D0 (even) as the data CDQ corresponding to the data DQ in response to the rising edge of data strobe CDQS signal corresponding to DQS signal at the timing P1. A first data latch section (even) (not shown) of the data latch circuit 17 latches the data D0 (even). The data D0 (even) shown in FIG. 2 indicates the data D0 (even). The data latch circuit 17 receives a data D1 as the data CDQ corresponding to the data DQ in response to the falling edge of the data strobe signal CDQS corresponding to the data strobe signal DQS at the timing P1. The second data latch section (odd) (not shown) of the data latch circuit 17 latches the data D1. The data D1 (odd) shown in FIG. 2 indicates the data D1 (odd). The data latch circuit 17 receives a data D2 as the data CDQ corresponding to the data DQ in response to the rising edge of data strobe CDQS corresponding to the data strobe DQS at the timing P2 in the first data latch section (even). The data D2 (even) shown in FIG. 2 indicates the data D2 (even). The data latch circuit 17 receives a data D3 (odd) as the data CDQ corresponding to the data DQ in response to the falling edge of the data strobe CDQS corresponding to the data strobe DQS at the timing P2 in the second data latch section (odd). The data D3 (odd) shown in FIG. 2 indicates the data D3 (odd). The data latch circuit 17 latches the data D0 (even) in the first data latch section and the data D1 (odd) in the second data latch section in parallel to the third data latch section (not shown) of the data latch circuit 17 in response to the rising edge of the internal clock signal ICLK at the timing T2. Then, the data latch circuit 17 outputs the latched data D0 (even) and data D1 (odd) as a data IDQ to the write buffer circuit 18. The data latch circuit 17 latches the data D2 (even) in the first data latch section and the data D3 (odd) in the second data latch section in parallel to the third data latch section of the data latch circuit 17 in response to the rising edge of the, internal clock signal ICLK at the timing T3. Then, the data latch circuit 17 outputs the latched data D2 (even) and data D3 (odd) as a data IDQ to the write buffer circuit 18.
The command decoder circuit 12 inputs the signals CCS, CRAS, CCAS, and CWE from the command receiving circuit 11. The command decoder circuit 12 outputs the active signal WBST (high level) in response to the rising edge of the internal clock signal ICLK at the timing T0 to the column control circuit 14. The command decoder circuit 12 outputs the active Y-address buffer control signal YAL (high level) as the one-shot pulse signal in response to the rising edge of the internal clock signal ICLK at the timing T2 to the Y-address buffer circuit 10 and the column control circuit 14. Then, the command decoder circuit 12 outputs the active Y-address buffer control signal NYAL (high level) as the one-shot pulse signal in response to the rising edge of the internal clock signal ICLK at the timing T3 to the Y-address buffer circuit 10 and the column control circuit 14. The Y-address buffer control signal YAL is the Y-address buffer control signal in the first burst portion, and the Y-address buffer control signal NYAL is the Y-address buffer control signal in the second burst portion. Because the length of the burst is 4, a period from the timing T2 to the timing T4 is the write burst period.
The column control circuit 14 inputs the Y-address buffer control signal YAL (the one-shot pulse signal) at the timing T2, when the signal WBST from the command decoder circuit 12 is active. At this time, the column control circuit 14 outputs the active write buffer control signal W0 (high level) as a start of the burst period to the write buffer circuit 18 in response to the Y-address buffer control signal YAL at the timing T2. The column control circuit 14 inputs the Y-address buffer control signal NYAL (the one-shot pulse signal) at the timing T3, when the signal WBST from the command decoder circuit 12 is active. Then, the column control circuit 14 outputs the inactive write buffer control signal W0 (low level) as an end of the burst period to the write buffer circuit 18 in synchronization with the internal clock signal ICLK at the timing T4.
As mentioned above, the burst period indicates the period during which the write buffer control signal W0 is active (high level). At this time, the write buffer circuit 18 operates as the buffer of data latch circuit 17. The write buffer circuit 18 outputs the data D0 (even) as the signal WBUS to the write amplifier circuit 19 and outputs the data D1 (odd) as the signal WBUS to the write amplifier circuit 20 in the burst period during timing T2 to T3 of the burst period. The write buffer circuit 18 outputs the data D2 (even as the signal WBUS to the write amplifier circuit 19 and outputs the data D3 (odd) as the signal WBUS to the write amplifier circuit 20 in the burst period during timing T3 to T4 of the burst period.
On the other hand, the address latch circuit 8 receives the address CADD (an address Y0) from the address receiving circuit 7 in response to the clock signal CLK at the time P0), and outputs it as an address IA in response to the rising edge of the internal clock signal ICLK at the timing T0. The Y-address buffer circuit 10 latches the address IA (address Y0) supplied from the address latch circuit 8 as the address IA in an address latch section (not shown) of the Y-address buffer circuit 10. According to the 2n-bit pre-fetch method, two kinds of Y-addresses of the address Y0 and the address Y1 are outputted as address YA at the timing T2. The address Y0 is the address corresponding to the column selection line CSL0 of the column selection line CSL connected to the memory cells of memory cell arrays 1 on the side of even. The address Y1 is the address corresponding to the column selection line CSL1 of the column selection line CSL connected to the memory cells of memory cell array 2 on the side of odd. Similarly to the timing T2, two kinds of Y-addresses of the address Y2 and the address Y3 are outputted as address YA at the timing T3. The address Y2 is the address corresponding to the column selection line CSL2 of the column selection line CSL connected to the memory cells of memory cell array 1 on the side of even. The address Y3 is the address corresponding to the column selection line CSL3 of the column selection line CSL connected to the memory cells of memory cell array 2 on the side of odd.
The relation of the address Y0 and the address Y2, the relation of the address Y1 and the address Y3 are indicated by the equation Y2=Y0+2 and Y3=Y1+2. Therefore, the Y-address buffer circuit 10 outputs the address Y0 (even) as the address YA to the column decoder circuit 21 and outputs the address Y1 (odd) as the address YA to the column decoder circuit 22 in response to the rising edge of the Y-address buffer control signal YAL at the timing T2. The Y-address buffer circuit 10 outputs the address Y2 (even) as the address YA to the column decoder circuit 21 and outputs the address Y3 (odd) as the address YA to the column decoder circuit 22 in response to the rising edge of the Y-address buffer control signal NYAL at the timing T3. The column control circuit 14 outputs the active column selection line control signal YSEL (high level) to the column decoder circuits 21 and 22 and outputs the active write amplifier control signal WAE (high level) to the write amplifier circuits 19 and 20 in response to the Y-address buffer control signal YAL at the timing T2. The column control circuit 14 outputs the active column selection line control signal YSEL (high level) to the column decoder circuits 21 and 22 and outputs the active write amplifier control signal WAE (high level) to the write amplifier circuits 19 and 20 in response to the Y-address buffer control signal NYAL at the timing T3. The column decoder circuit 21 sets a signal transferred through the column selection line CSL0 (even) to an active state (high level) in order to drive the column selection line CSL0 (even) at the timing T2 in response to the column selection line control signal YSEL at the timing T2. The column decoder circuit 22 sets a signal transferred through the column selection line CSL1 (odd) to an active state (high level) in order to drive the column selection line CSL1 (odd) at the timing T2 in response to the column selection line control signal YSEL at the timing T2. The column decoder circuit 21 sets a signal transferred through the column selection line CSL2 (even) to an active state (high level) in order to drive the column selection line CSL2 (even) at the timing T3 in response to the column selection line control signal YSEL at the timing T3. The column decoder circuit 22 sets a signal transferred through the column selection line CSL3 (odd) to an active state (high level) in order to drive the column selection line CSL3 (odd) at the timing T3 in response to the column selection line control signal YSEL at the timing T3.
The write amplifier circuit 19 outputs the signal WBUS (the data D0 (even)) from the write buffer circuit 18 as the write input data IO to the sense amplifier circuit 5 in response to the write amplifier control signal WAE at the timing T2. The sense amplifier circuit 5 outputs the write input data IO (the data D0 (even)) from the write amplifier circuit 19 to the bit line. The write input data IO (the data D0 (even)) is written in the memory cell (address Y0) connected to the bit line.
The write amplifier circuit 20 outputs the signal WBUS (the data D1 (odd)) from the write buffer circuit 18 as the write input data IO to the sense amplifier circuit 6 in response to the write amplifier control signal WAE at the timing T2. The sense amplifier circuit 6 outputs the write input data IO (the data D1 (odd)) from the write amplifier circuit 20 to the bit line. The write input data IO (the data D1 (odd)) is written in the memory cell (address Y1) connected to the bit line. The write amplifier circuit 19 outputs the writes bus WBUS (the data D2 (even)) from the write buffer circuit 18 as the write input data IO to the sense amplifier circuit 5 in response to the write amplifier control signal WAE at the timing T3. The sense amplifier circuit 5 outputs the write input data IO (the data D2 (even)) from the write amplifier circuit 19 to the bit line. The write input data IO (the data D2 (even)) is written in the memory cell (address Y2) connected to the bit line. The write amplifier circuit 20 outputs the writes bus WBUS (the data D3 (odd)) from the write buffer circuit 18 as the write input data IO to the sense amplifier circuit 6 in response to the write amplifier control signal WAE at the timing T3. The sense amplifier circuit 6 outputs the write input data IO (the data D3 (odd)) from the write amplifier circuit 20 to the bit line. The write input data IO (the data D3 (odd)) is written in the memory cell (address Y3) connected to the bit line.
Further next, the read operation the semiconductor memory device of the first conventional example will be described with reference to FIG. 3. The initial operation is same as the write operation. In case of the read operation, the command WEB indicates a read operation. The command receiving circuit 11 inputs the signals CSB, RASB, CASB, and WEB in synchronization with the clock signal CLK, and outputs the signals CCS, CRAS, CCAS, and CWE to the command decoder circuit 12. The address receiving circuit 7 inputs the address Y0 as address ADD in synchronization with the clock signal CLK, and outputs the address CADD (address Y0) to the address latch circuit 8.
Now the read operation will be described bellow referring to FIG. 1 and FIG. 3. The timing when the command receiving circuit 11 inputs the read command in synchronization with the clock signal CLK is supposed to be P0. The clock receiving circuit detects the rising edge of the clock signal CLK when the clock receiving circuit inputs the clock signal CLK at the timing P0, P1, P2, P3, P4, . . . . Then, the clock receiving circuit 11 outputs the internal clock signal ICLK as an one-shot pulse signal at the timing T0, T1, T2, T3, T4, . . . . The internal clock signal ICLK is outputted to have the time difference of (P0−T0), (P1−T1), (P2−T2), (P3−T3), (P4−T4), . . . to the clock signal CLK. The command decoder circuit 12 inputs the signals CCS, CRAS, CCAS, CWE from the command receiving circuit 11. The command decoder circuit 12 outputs the inactive signal WBST (low level) to the column control circuit 14 in response to the rising edge of the internal clock signal ICLK at the timing T0. The command decoder circuit 12 outputs the active Y-address buffer control signal YAL (high level) as the one-shot pulse signal in response to the rising edge of the internal clock signal ICLK at the timing T0 to the Y-address buffer circuit 10 and the column control circuit 14. Then, the command decoder circuit 12 outputs the active Y-address buffer control signal NYAL (high level) as the one-shot pulse signal to the Y-address buffer circuit 10 and the column control circuit 14 in response to the rising edge of the internal clock signal ICLK at the timing T1. The address latch circuit 8 receives the address CADD (an address Y0) from the address receiving circuit 7 in response to the clock signal CLK (the time P0) then, outputs the one as an address IA in response to the rising edge of the internal clock signal ICLK at the timing T0. The Y-address buffer circuit 10 latches the address IA (address Y0) from address latch circuit 8 as the address IA in an address latch section (not shown) of the Y-address buffer circuit 10. Similarly to the write operation, according to the 2n-bit pre-fetch method, two kinds of Y-addresses of the address Y0 corresponding to the column selection line CSL0 and the address Y1 corresponding to the column, selection line CSL1 are outputted as address YA at the timing T0. Also, like the write operation, two kinds of Y-addresses of the address Y2 corresponding to the column selection line CSL2 and the address Y3 corresponds to the column selection line CSL3 are outputted as address YA in the timing T1. Therefore, the Y-address buffer circuit 10 outputs the address Y0 (even) as the address YA to the column decoder circuit 21 and outputs the address Y1 (odd) as the address YA to the column decoder circuit 22 in response to the rising edge of the Y-address buffer control signal YAL at the timing T0. The Y-address buffer circuit 10 outputs the address Y2. (even) as the address YA to the column decoder circuit 21 and outputs the address Y3 (odd) as the address YA to the column decoder circuit 22 in response to the rising edge of the Y-address: buffer control signal NYAL at the timing T1. The column control circuit 14 outputs the active column selection line control signal YSEL (high level) to the column decoder circuits 21 and 22 in response to the Y-address buffer control signal YAL at the timing T0. The column control circuit 14 outputs the active column selection line control signal YSEL (high level) to the column decoder circuits 21 and 22 in response to the Y-address buffer control signal NYAL at the timing T1. The column decoder circuit 21 sets a signal transferred through the column selection line CSL0 (even) to an active state (high level) in order to drive the column selection line CSL0 (even) at the timing T0 in response to the column selection line control signal YSEL at the timing T0. The column decoder circuit 22 sets a signal transferred through the column selection line CSL1 (odd) to an active state (high level) in order to drive the column selection line CSL1 (odd) at the timing T0 in response to the column selection line control signal YSEL at the timing T0. The column decoder circuit 21 sets a signal transferred through the column selection line CSL2 (even) to an active state (high level) in order to drive the column selection line CSL2 (even) at the timing T1 in response to the column selection line control signal YSEL at the timing T1. The column decoder circuit 22 sets a signal transferred through the column selection line CSL3 (odd) to an active state (high level) in order to drive the column selection line CSL3 (odd) at the timing T1 in response to the column selection line control signal YSEL at the timing T1.
As described above, in the semiconductor memory device of the first conventional example the timings of the read operation, timings T0 and T1 at which the command decoder circuit 12 outputs the Y-address buffer control signals YAL and NYAL are earlier than the timings of the write operation by two clocks. That is, in the read operation, the timing of the column selection line CSL to be activated (the timing at which the signal transferred the column selection line CSL becomes active) is earlier than the timing in write operation by two clocks. Therefore, the data of the sense amplifier circuits 5 and 6 activated by the active command are destroyed by the column selection line CSL activated by the read command sometimes depending on the use circumstances (for example, the data length and the burst length). The technique disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-504129) is a circuit characterized by the improvement of yield of memory chip by shifting an extra time which can be used for tAA to more critical parameter tRCD. The tAA indicates a duration between the clock to the input of the read command at a setting to CAS LATENCY=1 and the output of all data (all data of eight data in the case of x8) to DQ PAD as in the expectation value. The tAA is used as the index which indicates the efficiency of the chip. The tRCD indicates duration between the clock to the input of active command and the clock to the input of the column command (the write command/read command).
The semiconductor memory device of a second conventional example is characterized by including above-mentioned technique in addition to the technique of the first conventional example FIG. 4 shows a circuit configuration of the semiconductor memory device in the second conventional example. The read operation of the memory operation will be described, like the first conventional example. The semiconductor memory device of the second conventional example is further composed of a mode exchange circuit 23 in addition to the configuration of the first conventional example. The mode exchange circuit 23 is connected to the command decoder circuit 12. The semiconductor memory device of the second conventional example carries out one of an ordinary operation mode and a column address delay operation mode. Whether the ordinary operation mode or the column address delay operation mode is determined in accordance with the use circumstance such as the data length and the burst length and is previously set to the mode exchange circuit 23. The ordinary operation mode indicates the write operation (see FIG. 2), and the read operation (see FIG. 3 of the semiconductor memory device of the first conventional example.
In the ordinary operation mode, the exchange circuit 23 outputs an active column address delay control signal LTAA (low level), to the command decoder circuit 12. In the second conventional example, the write operation and the read operation of the ordinary operation mode are carried out.
In the column address delay operation mode, the exchange circuit 23 output an active column address delay control signal LTAA (high level) to the command decoder circuit 12. In the second conventional example, the write operation and the read operation of the column address delay operation mode are carried out.
Next, the write operation of the column address delay operation mode in the second conventional example will be described. As shown in FIG. 5, the command decoder circuit 12 inputs the signals CCS, CRAS, CCAS, CWE as the write command from the command receiving circuit 11. The command decoder circuit 12 outputs the active signal WBST (high level) to the column control circuit 14 in response to the rising edge of the internal clock signal ICLK at the timing T0. When the column address delay control signal LTAA from the mode exchange circuit 23 is active, the command decoder circuit 12 outputs the active Y-address buffer, control signals YAL and NYAL (high level) to the Y-address buffer circuit 10 and the column control circuit 14 at a timing after a predetermined time, i.e., for the time of tDELAY compared with the ordinary operation mode. The predetermined time tDELAY is shorter than the time between the rising of the clock CLK and the rising of the next clock CLK and it is longer than the time between the rising of the internal clock signal ICLK and the falling of the internal clock signal ICLK. More specifically, in the column address delay, operation mode, the command decoder circuit 12 detects the rising edge of the internal clock signal ICLK at the timing T2 and outputs the active Y-address buffer control signal YAL (high level) to the Y-address buffer circuit 10 and the column control circuit 14 the time tDELAY after the detection. The command decoder circuit 12 detects the rising edge of the internal clock signal ICLK at the timing T3 and outputs the active Y-address buffer control signal NYAL (high level) to the Y-address buffer circuit 10 and the column control circuit 14 the time tDELAY after the detection. Therefore, the timing that the write buffer control signal W0 becomes active (high level) is delayed for the predetermined time tDELAY. Also, the timing that data IDQ (data D0 (even), D1 (odd), D2 (even), D3 (odd)) is outputted as the signal WBUS and the timing that the address YA (address Y0 (even), Y1 (odd),Y2, (even), Y3 (odd) is outputted are delayed for the predetermined time tDELAY. Further, the timing that the column selection line control signal YSEL becomes active (high level) and the timing that the signal transferred through the column selection line CSL (the column selection line CSL0 (even), CSL1 (odd), CSL2 (even), CSL3 (odd)) becomes active (high level) are delayed for the predetermined time tDELAY. Furthermore, the timing that the write amplifier control signal WAE becomes active (high level) the timing that the signal WBUS (the data D0 (even), D1 (odd), D2 (even), D3 (odd)) is outputted as write input data IO, and the timing that the write input data IO (the data D0 (even), D1 (odd), D2 (even), D3 (odd)) is written in the memory cell (addresses Y0, Y1, Y2, and Y3) connected to the bit lines are delayed for the predetermined time tDELAY.
Next, the read operation of the column address delay operation mode in the second conventional example will be described. As shown in FIG. 6, the command decoder circuit 12 inputs the signals CCS, CRAS, CCAS, and CWE as the read command from the command receiving circuit 11. The command decoder circuit 12 outputs the inactive signal WBST (low level) to the column control circuit 14 in response to the rising edge of the internal clock signal ICLK at the timing T0. When the column address delay control signal LTAA from the mode exchange circuit 23 is active, the command decoder circuit 12 outputs the active Y-address buffer control signals YAL and NYAL (high level) to the Y-address buffer circuit 10 and the column control circuit 14 at the timing after the predetermined time, i.e., the time of tDELAY compared with the ordinary operation mode More specifically, in the column address delay operation mode, the command decoder circuit 12 detects the rising edge of the internal clock signal ICLK at the timing T0 and outputs the active Y-address buffer control signal YAL (high level) to the Y-address buffer circuit 10 and the column control circuit 14 the time tDELAY after the detection. The command decoder circuit 12 detects the rising edge of the internal clock signal ICLK at the timing T1 and outputs the active Y-address buffer control signal NYAL (high level) to the Y-address buffer circuits 10 and the column control circuit 14 the time tDELAY after the detection. The command decoder circuit 12 detects the rising edge of the internal clock signal ICLK at the timing T1 and outputs the active Y-address buffer control signal NYAL (high level) to the Y-address buffer circuit 10 and the column control circuit 14 the time tDELAY after the detection Therefore, in the column address delay operation mode, the timing that address YA (the address Y0 (even), Y1 (odd), Y2 (even), Y3 (odd)) is outputted is delayed for the predetermined time tDELAY compared with the ordinary operation mode. Also, the timing that the column selection line control signal YSEL becomes active (high level) and the timing that the signal transferred through the column selection line CSL (the column selection line CSL0 (even), CSL1 (odd), CSL2 (even), CSL3 (odd)) becomes active (high level) is delayed for the predetermined time tDELAY compared with the ordinary operation mode. As a result, data cannot be destroyed in the read operation in the column address delay operation mode of the second conventional example.
Furthermore, because the timing that that the signal transferred through the column selection line CSL becomes active (high level) is delayed compared. with the ordinary operation mode, the tAA path from the sense amplifier circuits 5 and 6 to DQ PAD is delayed for the predetermined time tDELAY compared with the ordinary operation mode. In this way, during the read operation of the column address delay operation mode, the duration between the rising edge of the clock CLK and the activation of the column selection line CSL is increased by the predetermined time tDELAY compared with the ordinary operation mode. These results in that the time tRCD in the column address delay operation mode can be reduced compared with that of the ordinary operation mode by the predetermined time tDELAY, though tAA of the column address delay operation mode is increased compared with the done the ordinary operation mode by the predetermined time tDELAY. Although, the timing that Y-address buffer control signals YAL and NYAL become active (high level) is delayed for the predetermined time tDELAY compared with the ordinary operation mode in the column address delay operation mode, even if during the write operation. That is, during the read operation of the column address delay operation mode, the duration between the rising edge of the clock CLK at the time P0 and the activation of the column selection line CSL is increased by the predetermined time tDELAY compared with the ordinary operation mode. As a result, the time tWR of the column address delay operation mode is also increased compared with the one of the ordinary operation mode. The time tWR indicates the duration from a clock which is a second clock after the input of the write command to a clock to reset the word line, which is a clock to input a pre-charge command.
As described above, the semiconductor memory devices of the first and the second conventional examples do not have flexibility to use circumstance, such as a data length and a burst length.